A mechanism and set of rules that ensure multiple cached copies of shared memory locations in a multiprocessor or multicore system remain mutually consistent according to the chosen memory and coherence model, so that reads and writes behave predictably across caches.

Principle

Coherence protocols enforce invariants about the visibility of writes to the same memory location across caches: common approaches use states (e.g., MESI: Modified, Exclusive, Shared, Invalid), transitions on reads/writes, and messages (snooping on a bus or directory‑based) to implement either write‑invalidate or write‑update policies. The protocol must interact with the system’s memory consistency model and ordering guarantees.

Demonstration

Concrete instances: MESI family protocols used in snooping caches on a bus; MSI/MESIF variants; directory‑based coherence for large NUMA/massively multicore machines; write‑invalidate vs write‑update tradeoffs illustrated by a shared variable updated frequently vs read‑heavy sharing.

Misapplication

Confusing coherence with higher‑level consistency models—coherence ensures a single location’s updates are visible in a coherent way, but does not by itself guarantee global ordering required by sequential consistency. Assuming coherence removes need for synchronization: races and atomicity issues remain even with a correct coherence protocol.

Consequence

A correct coherence protocol simplifies reasoning about single‑location updates and permits more intuitive shared‑memory programming, but imposes bandwidth, latency, and scalability costs and shapes cache line migration and eviction behavior that affect performance.

Reversal

Non‑coherent or software‑managed caches (e.g., explicit message passing, distributed shared‑nothing) remove automatic hardware coherence: software or protocol layers must ensure consistency at application granularity, trading hardware complexity for scalability or explicit control.

Boundary

Applies to hardware and low‑level software that manage cached copies of shared memory in systems with coherent shared address spaces; it excludes higher‑level distributed cache coherence across machines without a shared physical address space (CDNs, web caches) and does not by itself define ordering constraints beyond per‑location coherence.

Semantic Tension

Tension between coherence (per‑location visibility) and consistency (global ordering); another tension is between write‑invalidate (lower coherence traffic for writers) and write‑update (lower read latency for sharers) approaches, plus interactions with relaxed memory models and performance needs.

Synthesis

A cache coherence protocol is the rule set and messaging/state machinery that keeps cached copies of the same memory locations consistent across processors, typically via state machines (MESI/MSI) and either snooping or directory schemes, balancing correctness for single‑location visibility against bandwidth and scalability costs while coexisting with the system’s memory consistency model.